Senior Digital Engineer with over 6+ years of expertise in High-Speed IP Integration, RTL Design, and FPGA Prototyping. Proven track record in integrating complex third-party IPs (Rambus MACsec, Synopsys PCIe Gen5) and achieving timing closure at 1.3GHz. Expert in bridging pre-silicon verification (HAPS) and post-silicon qualification (CP/FT) using industry-standard ATE (Advantest 93K), with a focus on de-risking system bring-up and optimizing verification cycles.