Yuan-Pin Huang
Staff Engineer | Digital IC Design & SoC Integration
Architecture Definition · Cross-Team Closure Criteria · RTL Design · SoC/IP Integration · FPGA Emulation · Silicon Bring-up
Executive Summary
MediaTek E9 / Staff Engineer with 10+ years of experience spanning ASIC RTL design, SoC/IP integration, FPGA/CPLD development, full-SoC emulation, physical-aware implementation, and design-driven silicon productization. Defines subsystem architecture boundaries, integration contracts, closure criteria, and pre-silicon de-risk plans across RTL, DV, DFT, APR, emulation, and post-silicon teams. Owned AXI-based SRAM controller subsystems across advanced-node modem SoCs, integrated 112G retimer/MACsec IP and PCIe Gen5 test-chip IP, and drove HAPS/Palladium-class validation milestones to reduce bring-up risk. Strong fit for Staff roles requiring architecture definition, technical risk review, cross-team sign-off readiness, and execution from pre-silicon definition through production ramp.
Core Competencies
Architecture Definition
Architecture Review
RTL Design
SoC / IP Integration
AXI3 / AMBA
SRAM Controller
Low-Power Control
PCIe Gen5 Test Chip
112G Retimer / MACsec
Lint / CDC
DFT / MBIST
Synthesis / STA Collaboration
Clock Constraints
Closure Criteria
Sign-off Readiness
HAPS / Palladium
FPGA Bring-up
Risk Decomposition
Post-Silicon Debug
Yield / DPPM Tracking
Professional Experience
MediaTek Inc.
Staff Engineer / Subsystem & Cross-Team Closure Owner
Charter: architecture-level definition, integration closure, pre-silicon de-risking, and design-aware productization across advanced-node modem SoCs, 112G retimer, PCIe Gen5 test chip, and AI accelerator programs; promoted to E9 Staff Engineer in 2026 after E8 Senior Design Engineer promotion in 2021.
- Architecture definition & review: Defined SRAM controller integration boundaries, AXI3 transaction behavior, 8-way interleave assumptions, low-power
SLEEPBpolicy, CDC/DFT/MBIST expectations, and timing-constraint handoff criteria with SoC, DV, DFT, and APR stakeholders. - Cross-team closure framework: Established practical closure checkpoints for RTL quality, CDC cleanliness, MBIST/DFT insertion readiness, synthesis constraints, APR handoff, emulation milestones, and post-silicon debug coverage to keep subsystem risks visible before tape-out and bring-up.
- Memory subsystem ownership: Owned AXI3-compliant SRAM controller subsystems across MT6980 / MT6990 / MT2737 / MT6986 / MT6988 / MT2739 modem programs, covering RTL design, controller implementation, verification, Lint/CDC, MBIST/DFT insertion, synthesis, clock-tree constraints, and APR timing-closure collaboration.
- 1408KB SRAM controller: Designed and delivered a single-port TSMC SRAM controller with 8-way interleave and automatic low-power
SLEEPBmanagement; closed timing at 728 MHz for a 200K+ cell, 350K μm² subsystem on N4 modem products. - 512KB SRAM controller: Previously delivered AXI3-compliant single-port SRAM controller at 533 MHz, covering 50K+ cells and 175K μm² area, with full RTL-to-implementation ownership.
- 112G retimer / MACsec sign-off readiness: Integrated Rambus MACsec subsystem and defined front-to-backend closure checkpoints for DFT insertion, synthesis, clock constraints, congestion/timing risk, and APR handoff; coordinated with APR stakeholders to achieve timing closure at 1.308 GHz on a 5M+ cell, 3.5M μm² block.
- Emulation de-risk plan: Translated architecture and bring-up risks into HAPS/Palladium validation milestones for modem and retimer projects; connected four HAPS-80 systems through HT3 cables for whole-chip verification and system-level debug readiness.
- Bring-up risk reduction: Early-ported low-power behavior into FPGA emulation to validate power-state assumptions before silicon; integrated thermal controller logic and coordinated sensor-position planning with SoC and physical-design stakeholders.
- Design-aware productization readiness: Converted design intent into production test readiness by driving Day-0 coverage/pass-rate tracking, JTAG/UART/GPIO testability verification, probe card/load board capability definition, test-flow/program definition, yield/DPPM tracking, and MP flow/program release for MT6986 / MT2739 and TPU v7 programs.
Digital IC Design Engineer
MT66007 PCIe Gen5 test chip, third-party IP verification support, Palladium/HAPS emulation environment setup; started as E7 Design Engineer.
- PCIe Gen5 integration contract: Integrated Synopsys PCIe Gen5 MAC into ASIC test-chip environment and aligned MAC/PHY/DV/APR interfaces, Lint/CDC expectations, MBIST insertion scope, local VIP setup, and PHY/MAC co-verification criteria.
- Cross-functional closure: Partnered with DV, PHY, BE, and APR teams to close verification and implementation risks, pass PHY+MAC test plans, and reach timing closure at 1 GHz.
- Emulation enablement: Supported ASIC project emulation tasks and helped build Synopsys FPGA environment components for faster system-level validation and debug.
Wiwynn Corp.
Server FPGA / CPLD Design Engineer
Hyperscale server CPLD/FPGA control logic, platform debug architecture, and FPGA-based AI demonstration platforms.
- Server control logic: Developed CPLD/FPGA logic for server power control, LED control, debug interfaces, I2C/SPI connectivity, and BMC communication on server boards.
- Debug architecture: Architected and implemented an OCP-compliant debug card using AVR microcontrollers, improving engineering diagnostics and platform bring-up efficiency.
- FPGA AI demonstration: Built Intel Altera FPGA-based server platform capabilities for AI training demos using OpenVINO / TensorFlow workloads, including CNN, GNN, and reinforcement-learning demonstrations for Computex.
Selected Silicon Programs
MT6986 / MT6988 / MT2739 Modem SoCs: 1408KB AXI3 SRAM controller architecture boundary, low-power memory policy, thermal-controller integration, full-SoC emulation de-risking, silicon bring-up, and production ramp.
MT6980 / MT6990 / MT2737 Modem SoCs: 512KB AXI3 SRAM controller ownership, integration closure criteria, and full-SoC FPGA emulation risk coverage.
MT3775 112G Retimer: Rambus MACsec integration with sign-off readiness across large-block synthesis, DFT insertion, clock constraints, APR handoff, and 1.308GHz timing closure.
MT66007 PCIe Gen5 Test Chip: Synopsys PCIe Gen5 MAC integration contract, Lint/CDC/MBIST cleanup, VIP setup, PHY/MAC verification criteria, and 1GHz timing closure.
TPU v7: Production test readiness, test-flow/program definition, yield/DPPM tracking, and MP flow/program release from a design-for-productization perspective.
Wiwynn Server Platforms: CPLD/FPGA power/debug control, OCP debug-card architecture, and Intel Altera FPGA AI server demos.
Technical Skills
Languages
Verilog, SystemVerilog, Python, Tcl, Shell, C/C++
Design Domains
Architecture boundary definition, architecture review support, RTL design, SRAM controller implementation, low-power memory control, SoC/IP integration, thermal controller integration
Front-End Flow
Lint, CDC/RDC, local VIP setup, PHY/MAC co-verification, synthesis, LEC, DFT/MBIST insertion, clock and timing constraints
Implementation
Physical-aware RTL, synthesis handoff, APR collaboration, timing-closure debug, closure criteria review, sign-off readiness support, clock-tree constraint development
Emulation / FPGA
Palladium, Synopsys HAPS, multi-FPGA partitioning awareness, Xilinx FPGA prototyping, Lattice CPLD, Intel Altera FPGA tools
Protocols / IP
AXI3 / AMBA, PCIe Gen5, MACsec, I2C, SPI, JTAG, UART, GPIO
Tools
Synopsys VCS / Verdi / Design Compiler / SpyGlass / PrimeTime, Cadence Genus / Innovus / LEC, Xilinx Vivado / Siemens 0in
Education
National Taiwan Normal University (NTNU)
M.S., Computer Science and Information Engineering
National Taipei University of Education (NTUE)
B.S., Computer Science